37.4.38 I3CxMWS
Note:
- This register follows the definition of GETMXDS CCC Maximum Write Speed Byte format as per the MIPI I3C 1.1.1 Specification. The Controller can read this byte during GETMXDS CCC.
- The I3C module on this device
does not support Format 3 of GETMXDS CCC and does not support an optional
Defining Byte. It is highly recommended for the user to program MWS[3] bit
to
0. - To ensure expected behavior,
this register should only be written when the module is disabled (EN =
0).
| Name: | I3CxMWS |
| Address: | 0x0AC, 0x0DF |
Maximum Write Speed
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| MWS[7:4] | MWS[3] | MWS[2:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 10:4 – MWS[7:4] MIPI Reserved
Bit 3 – MWS[3] Defining Byte Support (2)
| Value | Description |
|---|---|
| 1 | This I3C module supports an optional Defining Byte for GETMXDS CCC |
| 0 | This I3C module does not support an optional Defining Byte for GETMXDS CCC (recommended) |
Bits 2:0 – MWS[2:0] Maximum Sustained Write Speed for Non-CCC Messages
| Value | Description |
|---|---|
| 111 | MIPI Reserved |
| 110 | MIPI Reserved |
| 101 | MIPI Reserved |
| 100 | 2 MHz |
| 011 | 4 MHz |
| 010 | 6 MHz |
| 001 | 8 MHz |
| 000 | FSCL Max |