37.4.9 I3CxPIR1
Note:
- Will not self-clear after the event. The user must clear this bit to re-arm.
- In case of a race condition, user writes always take precedence over hardware events.
| Name: | I3CxPIR1 |
| Address: | 0x08B, 0x0BE |
General Interrupt Flag 1
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TCOMPIF | DACHIF | IBIDONEIF | |||||||
| Access | R/W/HS | R/W/HS | R/W/HS | ||||||
| Reset | 0 | 0 | 0 |
Bit 7 – TCOMPIF Transaction Complete Interrupt Flag(1)
| Value | Description |
|---|---|
| 1 | Private/I2C/IBI Transaction completed (This module was addressed and Stop or Restart condition was detected) |
| 0 | Private/I2C/IBI Transaction not completed or not started |
Bit 6 – DACHIF Dynamic Address Changed Interrupt Flag(1)
| Value | Description |
|---|---|
| 1 | The I3CxDADR Dynamic Address was assigned, cleared, or changed |
| 0 | The I3CxDADR Dynamic Address was not assigned, cleared, or changed |
Bit 5 – IBIDONEIF In-Band Interrupt Done Interrupt Flag(1)
| Value | Description |
|---|---|
| 1 | In-Band Interrupt request completed |
| 0 | In-Band Interrupt request not completed or not started |
