36.7.12 USB TX Interrupt Enable Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | INTRTXE |
| Offset: | 0x1006 |
| Reset: | 0x0000 |
| Property: | PAC Write-Protection |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EP6TXEN | EP5TXEN | EP4TXEN | EP3TXEN | EP2TXEN | EP1TXEN | EP0TXEN | EP0EN | ||
| Access | R/HS | R/HS | R/HS | R/HS | R/HS | R/HS | R/HS | R/HS | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 1, 2, 3, 4, 5, 6, 7 – EPnTXEN Endpoint ‘n’ Transmit Interrupt Enable bits
| Value | Description |
|---|---|
| 0 | Endpoint Transmit interrupt events are not enabled |
| 1 | Endpoint Transmit interrupt events are enabled |
Bit 0 – EP0EN Endpoint 0 Interrupt Enable bit
| Value | Description |
|---|---|
| 0 | Endpoint 0 interrupt events are not enabled |
| 1 | Endpoint 0 interrupt events are enabled |