36.7.26 USB Miscellaneous Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | MISC |
| Offset: | 0x1061 |
| Reset: | 0x0000 |
| Property: | PAC Write-Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TXEDMA | RXEDMA | ||||||||
| Access | R | R | |||||||
| Reset | 0 | 0 |
Bit 1 – TXEDMA TX Endpoint DMA Assertion Control bit
| Value | Description |
|---|---|
| 0 | DMA_REQ signal for all IN endpoints will be deasserted when MAXP bytes have been written to an endpoint. This is Late mode. |
| 1 | DMA_REQ signal for all IN endpoints will be deasserted when MAXP-8 bytes have been written to an endpoint. This is Early mode. |
Bit 0 – RXEDMA RX Endpoint DMA Assertion Control bit
| Value | Description |
|---|---|
| 0 | DMA_REQ signal for all IN endpoints will be deasserted when MAXP bytes have been written to an endpoint. This is Late mode. |
| 1 | DMA_REQ signal for all IN endpoints will be deasserted when MAXP-8 bytes have been written to an endpoint. This is Early mode. |