36.7.28 USB RX FIFO Size Register

RXFIFOSZ controls the size of the selected RX endpoint FIFO.

Table 36-28. Register Bit Attribute Legend
Symbol Description Symbol Description Symbol Description
R Readable bit HC Cleared by Hardware (Grey cell) Unimplemented
W Writable bit HS Set by Hardware X Bit is unknown at Reset
K Write to clear S Software settable bit
Name: RXFIFOSZ
Offset: 0x1063
Reset: 0x0000
Property: PAC Write-Protection

Bit 76543210 
    DPBFIFOSZ[3:0] 
Access R/WR/WR/WR/WR/W 
Reset 00000 

Bit 4 – DPB RX Endpoint Double-packet Buffering Control bit

ValueDescription
0 Double-packet buffer is not supported
1 Double-packet buffer is supported. This doubles the size set in RXFIFOSZ.

Bits 3:0 – FIFOSZ[3:0] RX Endpoint FIFO packet size bits

The maximum packet size to allowed for (before any splitting within the FIFO of Bulk/High-Bandwidth packets prior to transmission)

ValueDescription
1111 Reserved
1010 Reserved
1001 4096 bytes
1000 2048 bytes
0111 1024 bytes
0110 512 bytes
0101 256 bytes
0100 128 bytes
0011 64 bytes
0010 32 bytes
0001 16 bytes
0000 8 bytes