36.7.58 PHY Control Register 24
Note: The USB PHY values must be loaded from the CAL OTP area into
the USB PHY registers by software, before enabling the USB, to achieve the specified
accuracy.
Symbol | Description | Symbol | Description | Symbol | Description |
---|---|---|---|---|---|
R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
K | Write to clear | S | Software settable bit | — | — |
Name: | PHY24 |
Offset: | 0x1524 |
Reset: | 0x0000000C |
Property: | PAC Write-Protection |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
Access | |||||||||
Reset |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
HSDRIVST[1:0] | HSPREEMPST[2:0] | PREEMPHEN | OTGPDN | HSSLEW | |||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 |
Bits 7:6 – HSDRIVST[1:0] HS Transmit Driver Strength
Sets the HS transmit driver strength.
Settings include the lower bits (PHY24.6:7) and the upper bit (PHY28.0).
Value | Description |
---|---|
111 | Strongest drive strength |
000 | Weakest drive strength |
Bits 5:3 – HSPREEMPST[2:0] HS Transmit Pre-Emphasis Strength
Sets the HS transmit pre-emphasis strength.
Value | Description |
---|---|
11 | Slowest Slew Rate |
10 | - |
01 | - |
00 | Fastest Slew Rate |
Bit 2 – PREEMPHEN HS Transmit Pre-Emphasis Enable
Enable half-bit pre-emphasis for HS transmit.
Value | Description |
---|---|
1 | Enable |
0 | Disable |
Bit 1 – OTGPDN ODT Power Down
Sets the ODT power down.
Value | Description |
---|---|
1 | On |
0 | Off |
Bit 0 – HSSLEW HS Slew Rate
Sets the HS slew rate.
Settings include the lower bits (PHY20.6:7) and the upper bit (PHY24.0).
Value | Description |
---|---|
111 | Fastest rise/fall time |
010 | Middle slew rate |
001 | Slowest rise/fall time |
000 | Reserved |