36.7.39 USB DMA Channel x Control Register

Table 36-39. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	DMAxCTRL
Offset:	0x1204 + x*0x0A [x=0..7]
Reset:	0x0000000000
Property:	PAC Write-Protection


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
						DMABRSTM[1:0]		DMAERR
Access						R/W	R/W	R/W
Reset						0	0	0


Bit	7	6	5	4	3	2	1	0
	DMAEP[3:0]				DMAIE	DMAMODE	DMADIR	DMAEN
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 10:9 – DMABRSTM[1:0] DMA Burst Mode Selection bit

Value	Description
11	Burst Mode 3: INCR16, INCR8, INCR4 or unspecified length
10	Burst Mode 2: INCR8, INCR4 or unspecified length
01	Burst Mode 1: INCR4 or unspecified length
00	Burst Mode 0: Bursts of unspecified length

Bit 8 – DMAERR DMA Bus Error bit

Value	Description
0	The software writes this to clear the error
1	A bus error has been observed on the input

Bits 7:4 – DMAEP[3:0] DMA Endpoint Assignment bits

These bits hold the endpoint that the DMA channel is assigned to. Valid values are 0-7.

Bit 3 – DMAIE DMA Interrupt Enable bit

Value	Description
0	Interrupt is disabled for this channel
1	Interrupt is enabled for this channel

Bit 2 – DMAMODE DMA Transfer Mode bit

Value	Description
0	DMA Mode0 Transfers
1	DMA Mode1 Transfers

Bit 1 – DMADIR DMA Transfer Direction bit

Value	Description
0	DMA Write (RX endpoint)
1	DMA Read (TX endpoint)

Bit 0 – DMAEN DMA Enable bit

Value	Description
0	Disable the DMA transfer
1	Enable the DMA transfer and start the transfer

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