36.7.49 PHY Control Register 00
Note: The USB PHY values must be loaded from the CAL OTP area into
the USB PHY registers by software, before enabling the USB, to achieve the specified
accuracy.
Symbol | Description | Symbol | Description | Symbol | Description |
---|---|---|---|---|---|
R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
K | Write to clear | S | Software settable bit | — | — |
Name: | PHY00 |
Offset: | 0x1500 |
Reset: | 0x00000019 |
Property: | PAC Write-Protection |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
Access | |||||||||
Reset |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
RXPHSSEL[2:0] | SLEWRATE[1:0] | PREEMP[2:0] | |||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
Bits 7:5 – RXPHSSEL[2:0] RX Clock Phase Select
The delay associated with each step is 256ps.
Value | Description |
---|---|
111 | Represents the latest phase (7 * 256ps) |
110 | - |
100 | - |
011 | - |
010 | - |
001 | - |
000 | Represents the earliest phase (0 * 256ps) |
Bits 4:3 – SLEWRATE[1:0] Adjustment for FS/LS Slew Rate
Value | Description |
---|---|
11 | Slowest Slew Rate |
10 | - |
01 | - |
00 | Fastest Slew Rate |
Bits 2:0 – PREEMP[2:0] Pre-Emphasis Setting
Value | Description |
---|---|
111 | Enable pre-emphasis always |
110 | Enable pre-emphasis during chirp and non-chirp |
100 | Enable pre-emphasis during non-chirp |
011 | Enable pre-emphasis during SOF and EOP and chirp |
010 | Enable pre-emphasis during chirp |
001 | Enable pre-emphasis during SOF and EOP |
000 | Disable pre-emphasis |