36.7.31 USB Endpoint Info Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | EPIINFO |
| Offset: | 0x1078 |
| Reset: | 0x0000 |
| Property: | PAC Write-Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RXENDPOINTS[3:0] | TXENDPOINTS[3:0] | ||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | |
Bits 7:4 – RXENDPOINTS[3:0] Included RX Endpoint bits
This read-only register gives the number of RX endpoints in the design. For the PIC32CK SG/GC family, this number is 7.
Bits 3:0 – TXENDPOINTS[3:0] Included TX Endpoint bits
These read-only bits provide the number of TX endpoints in the design. For the PIC32CK SG/GC family, this number is 7.