36.7.8 Synchronization Busy Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | SYNCBUSY |
| Offset: | 0x001C |
| Reset: | 0x0000 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| T1MSEN | ENABLE | SWRST | |||||||
| Access | R/HC/HS | R/HC/HS | R/HC/HS | ||||||
| Reset | 0 | 0 | 0 |
Bit 2 – T1MSEN T1MS Enable busy bit
Note: Software must poll this bit to know when the operation completes.
| Value | Description |
|---|---|
| 0 | T1MSEN synchronization is NOT busy |
| 1 | T1MSEN synchronization is busy |
Bit 1 – ENABLE Enable Busy bit
Note: Software must poll this bit to know when the operation completes.
| Value | Description |
|---|---|
| 0 | ENABLE synchronization is NOT busy |
| 1 | ENABLE synchronization is busy |
Bit 0 – SWRST Software Reset Busy bit
Note: Software must poll this bit to know when the operation completes.
| Value | Description |
|---|---|
| 0 | SWRST synchronization is NOT busy |
| 1 | SWRST synchronization is busy |