36.7.23 USB TX End Point Double Packet Buffer Disable Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | TXDPKTBUFDIS |
| Offset: | 0x1342 |
| Reset: | 0x0000 |
| Property: | PAC Write-Protection |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EP6TXD | EP5TXD | EP4TXD | EP3TXD | EP2TXD | EP1TXD | EP0TXD | |||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 1, 2, 3, 4, 5, 6, 7 – EPnTXD TX Endpoint 'n' Double Packet Buffer Disable bits
| Value | Description |
|---|---|
| 0 | TX double packet buffering is enabled for endpoint 'n' |
| 1 | TX double packet buffering is disabled for endpoint 'n' |