36.7.37 USB Soft Reset Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | SOFTRST |
| Offset: | 0x107F |
| Reset: | 0x0000 |
| Property: | PAC Write-Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| NRSTX | NRST | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
Bit 1 – NRSTX Reset of XCLK Domain bit
| Value | Description |
|---|---|
| 0 | Normal operation |
| 1 | Reset the XCLK domain, which is clock recovered from the received data by the PHY |
Bit 0 – NRST Reset of CLK Domain bit
| Value | Description |
|---|---|
| 0 | Normal operation |
| 1 | Reset the CLK domain, which is clock recovered from the peripheral bus |