36.7.51 PHY Control Register 08
Note: The USB PHY values must be loaded from the CAL OTP area into
the USB PHY registers by software, before enabling the USB, to achieve the specified
accuracy.
Symbol | Description | Symbol | Description | Symbol | Description |
---|---|---|---|---|---|
R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
K | Write to clear | S | Software settable bit | — | — |
Name: | PHY08 |
Offset: | 0x1508 |
Reset: | 0x00000007 |
Property: | PAC Write-Protection |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
Access | |||||||||
Reset |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
SQUELCH | |||||||||
Access | R/W | ||||||||
Reset | 1 |
Bit 0 – SQUELCH RX Squelch Trigger Point Set
Sets the upper bit of the RX squelch trigger point configuration.
Settings include lower bits (PHY04.5:7) and upper bit the upper bit (PHY08.0).
Value | Description |
---|---|
1111 | 200 mV |
1110 | 125 mV |
1101 | 187.5 mV |
1100 | 150 mV (default) |
1011 | 175 mV |
1010 | 100 mV |
1001 | 162.5 mV |
1000 | Reserved |
0111 | Reserved |
0110 | 75 mV |
0101 | 137 mV |
0100 | 100 mV |
0011 | 162.5 mV |
0010 | 87.5 mV |
0001 | Reserved |
0000 | 112.5 mV |