36.7.7 Status Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | STATUS |
| Offset: | 0x0018 |
| Reset: | 0x0000 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| VREGRDY | PHYON | PHYRDY | |||||||
| Access | R/HC/HS | R/HC/HS | R/HC/HS | ||||||
| Reset | 0 | 0 | 0 |
Bit 2 – VREGRDY USB Voltage Regulator status
| Value | Description |
|---|---|
| 0 | Voltage Regulator output is off |
| 1 | Voltage Regulator output is on |
Bit 1 – PHYON PHY Power State
| Value | Description |
|---|---|
| 0 | PHY is in off (low power state) |
| 1 | PHY is in on (operational power state) |
Bit 0 – PHYRDY PHY Ready
| Value | Description |
|---|---|
| 0 | PHY is NOT Ready for USBCORE activity |
| 1 | PHY is ready for USBCORE activity |