11.2.35 CANx Transmit Event FIFO Status Register

Note:
  1. These bits are read-only and reflect the status of the FIFO.

Legend: R = Readable bit; S = Settable bit; HC = Hardware Clearable bit

Name: CxTEFSTA
Offset: 0x5C4, 0x704

Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
     TEFOVIFTEFFIFTEFHIFTEFNEIF 
Access R/S/HCRRR 
Reset 0000 

Bit 3 – TEFOVIF Transmit Event FIFO Overflow Interrupt Flag bit

ValueDescription
1 Overflow event has occurred
0 No Overflow event has occurred

Bit 2 – TEFFIF  Transmit Event FIFO Full Interrupt Flag bit(1)

ValueDescription
1 FIFO is full
0 FIFO is not full

Bit 1 – TEFHIF  Transmit Event FIFO hALF Full Interrupt Flag bit(1)

ValueDescription
1 FIFO is ≥ half full
0 FIFO is < half full

Bit 0 – TEFNEIF  Transmit Event FIFO Not Empty Interrupt Enable Flag bit(1)

ValueDescription
1 FIFO is not empty
0 FIFO is empty