49.17 DFLL48M Electrical Specifications

Table 49-21. DFLL48M (Digital Frequency Locked Loop) Electrical Specifications
AC CHARACTERISTICS			Standard Operating Conditions: VDD = AVDD = 1.62V to 3.63V (unless otherwise stated) Operating temperature: -40°C ≤ T_A ≤ +85°C for Industrial
Param. No.	Symbol	Characteristics	Min.	Typ.	Max.	Units	Conditions
DFLL48M (Open Loop)^(1,2)
DFLL_1	DFLL48M_OL_F_OUT	DFLL48M Open Loop Clock Frequency	45.6	46.4	47	MHz	LDO Mode, Performance Level 0 Mode
DFLL_1A			47.4	47.9	48.5		LDO Mode, Performance Level 2 Mode
DFLL_1B			45.1	46.4	47.3		BUCK Mode, Performance Level 0 Mode
DFLL_1C			47.3	47.9	48.6		BUCK Mode, Performance Level 2 Mode
DFLL_9	DFLL48M_OL_SRT	Start-Up (Ready bit valid)	—	—	11	µs	Performance Level 0 Mode
DFLL_9A	DFLL48M_OL_SRT	Start-Up (Ready bit valid)	—	—	10	µs	Performance Level 2 Mode
DFLL48M (Closed Loop) (3,4)
DFLL_11	DFLL48M_CL_F_IN	DFLL48M Closed loop Input Frequency Range	0.732	32.768	33	kHz	-
DFLL_13	DFLL48M_CL_F_OUT	DFLL48M Closed Loop Clock Frequency	47.7	48	48.3	MHz	LDO Mode, Performance Level 0 Mode, XOSC32 32.768 kHz PPM≤100
DFLL_13A			47.8	48	48.2		LDO Mode, Performance Level 2 Mode, XOSC32 32.768 kHz PPM≤100
DFLL_13B			47.2	48	48.9		BUCK Mode, Performance Level 0 Mode, XOSC32 32.768 kHz PPM≤100
DFLL_13C			47.7	48	48.3		BUCK Mode, Performance Level 2 Mode, XOSC32 32.768 kHz PPM≤100
DFLL_15	DFLL48M_CL_Jitter	DFLL48M Period Jitter Pk-to-Pk	—	—	2	%	LDO Mode, Performance Level 0 Mode, f_EXTERNAL=32.768 kHz @ ≤100ppm
DFLL_15A			—	—	1		LDO Mode, Performance Level 2 Mode, f_EXTERNAL=32.768 kHz @ ≤100ppm
DFLL_15B			—	—	13		LDO Mode, Performance Level 0 Mode, f_EXTERNAL=32.768 kHz @ ≤100ppm
DFLL_15C			—	—	4		LDO Mode, Performance Level 2 Mode, f_EXTERNAL=32.768 kHz @ ≤100ppm
DFLL_21	DFLL48M_CL_SRT⁽⁵⁾	DFLL48M Closed Loop Mode Lock Time	—	—	2074	µs	Performance Level 0 Mode, f_EXTERNAL=32.768 kHz @ ≤100ppm
DFLL_21A	DFLL48M_CL_SRT⁽⁵⁾	DFLL48M Closed Loop Mode Lock Time	—	—	853	µs	Performance Level 2 Mode, f_EXTERNAL=32.768 kHz @ ≤100ppm
Note: In Open Loop mode, the DFLL48M clock will be determined by the values written to the DFLL Coarse and the DFLL Fine bit fields (DFLLVAL.COARSE and DFLLVAL.FINE) in the DFLL Value register. Using the "DFLL48M COARSE" value from the NVM Software Calibration Area in DFLLVAL.COARSE helps to output a frequency close to 48MHz. Not recommended for functional USB operation, SOF sync start-up only. In Closed loop mode the DFLL48M can use a variety of clock sources. The DFLL48M can be trimmed using register DFLLMUL. To ensure that the device stays within the maximum allowed clock frequency, any reference clock for DFLL48M in close loop must be within a 2% error accuracy. DFLLMUL = 1464, DFLLCTRL.BPLCKC = 1: only fine value change, coarse value locked to the reset value. DFLLCTRL.QLDIS = 0: quick lock enable, DFLLCTRL.CCDIS = 1: Enabling chill cycles might double the lock time. DFLLMUL.FSTEP = 10 : Max fine step size, divided or dividing into two parts, search. 10 is a optimum value.