49.33 USB Electrical Specifications

Table 49-46. USB Electrical Specifications
AC CHARACTERISTICS			Standard Operating Conditions: VDD = AVDD = 1.62V to 3.63V (unless otherwise stated) Operating temperature: -40°C ≤ T_A ≤ +85°C for Industrial
Param. No.	Symbol	Characteristics	Min.	Typ.	Max.	Units	Conditions
USB_1	VUSB	USB Transceiver Voltage	3	—	3.6	V	—
VBUS Supply
USB_3	VBUS	High-power Port	4.75	—	5.25	V	500 mA Load
USB_5	VBUS	Low-power Port	4.4	—	5.25	V	100 mA Load
USB_7	VILUSB	Input Low Voltage for USB Buffer	—	—	0.8	V	—
USB_9	VIHUSB	Input High Voltage for USB Buffer	2	—	—	V	—
USB_11	VDIFS	Differential Input Sensitivity	0.2	—	—	V	The difference between D+ and D- must exceed this value while VCM is met
USB_13	VCM	Differential Common Mode Range	0.8	—	2.5	V	V_USB = 3.0V-to-3.6V
USB_15	ZOUT	Driver Output Impedance	28	—	44	Ω	—
USB_17	VOLUSB	Voltage Output Low	—	—	0.3	V	1.425 kΩ load connected to V_USB = 3.6V
USB_19	VOHUSB	Voltage Output High	2.8	—	—	V	14.25 kΩ load connected to ground w/V_USB = 3.0V
USB_23	USBCLKS	USB Clock Source (1) f_{GCLK_USB} of 48 MHz ± 0.25%	—	48	—	MHz	f_{GCLK_USB} = 48 MHz ± 0.25%
USB_25	USB_AHB	Min. AHB Clock for USB operations	12	—	—	MHz	—
Note: External Crystal or clock oscillator ≤ 50 ppm with FDPLL96M only for f_{GCLK_USB} of 48 MHz ± 0.25%.

Table 49-47. USB Clocks Configuration
USB Clock configuration			Standard Operating Conditions: VDD = AVDD = 1.62V to 3.63V (unless otherwise stated) Operating temperature: -40°C ≤ T_A ≤ +85°C for Industrial
Param. No.	Symbol	Characteristics	Device mode operation	Host mode operation
USB_31	USB_GCLK_SRC	DFLL48M Open loop	No	No
		DFLL48M Close loop, Ref. internal OSC source	No	No
		DFLL48M Close loop, Ref. external XOSC source	Yes	No
		DFLL48M Close loop, Ref. SOF (USB recovery mode)	Yes ⁽¹⁾	N/A
		FDPLL96M internal OSC	No	No
		FDPLL96M external OSC (with FDPLL96M reference clock < 1MHz)	Yes	No
		FDPLL96M external OSC (with FDPLL96M reference clock >1MHz)	Yes ⁽²⁾	Yes
Note: When using DFLL48M in USB recovery mode, the Fine Step value must be 0x0A to guarantee a USB clock at +/-0.25% before 11ms after a resume. Only usable in LDO regulator mode. FDPLL96M lock time is short when the clock frequency source is high (> 1 MHz). Thus, FDPLL96M and external OSC can be stopped during USB suspend mode to reduce consumption and guarantee a USB resume signal time, refer to “USB specification” for additional information.