49.3 Power Supply

Table 49-7. Power Supply Electrical Specifications
DC CHARACTERISTICS				Standard Operating Conditions: VDD=AVDD = 1.62V to 3.63V (unless otherwise stated) Operating temperature: -40°C ≤ T_A ≤ +85°C for Industrial
Param. No.	Symbol	Characteristics		Min.	Typ.	Max.	Units	Conditions
REG_1	VDDCORE_C_IN ⁽⁵⁾	VDDCORE Input Bypass parallel Capacitor pair		0.8	1	1.2	µF	Bulk Ceramic or solid Tantalum with ESR <0.5Ω
REG_1	VDDCORE_C_IN ⁽⁵⁾	VDDCORE Input Bypass parallel Capacitor pair		80	100	—	nF	Ceramic XR7 with ESR <0.5Ω
REG_3	VDDPLL_C_IN ⁽⁵⁾	VDDPLL Input Bypass parallel Capacitor pair		0.8	1	1.2	µF	Bulk Ceramic or solid Tantalum with ESR <0.5Ω
REG_3	VDDPLL_C_IN ⁽⁵⁾	VDDPLL Input Bypass parallel Capacitor pair		80	100	—	nF	Ceramic XR7 with ESR <0.5Ω
REG_5	VDD_C_IN ⁽⁵⁾	VDD Input Bypass parallel Capacitor pair		80	100	—	nF	Ceramic XR7 with ESR <0.5Ω on all VDD pins
REG_9	VREFx_C_IN ⁽⁵⁾	External VREFA/VREFB Input Bypass parallel Capacitor pair		3.76	4.7	—	µF	Bulk Ceramic or solid Tantalum with ESR <0.5Ω
REG_9	VREFx_C_IN ⁽⁵⁾	External VREFA/VREFB Input Bypass parallel Capacitor pair		80	100	—	nF	Ceramic XR7 with ESR <0.5Ω
REG_17	AVDD_C_IN ⁽⁵⁾	AVDD Input Bypass parallel Capacitor pair		8	10	—	µF	Bulk Ceramic or solid Tantalum with ESR <0.5Ω
REG_17	AVDD_C_IN ⁽⁵⁾	AVDD Input Bypass parallel Capacitor pair		80	100	—	nF	Ceramic XR7 with ESR <0.5Ω on all AVDD pins
REG_23	AVDD_L_EXT ⁽¹⁾	AVDD series Ferrite Bead DCR (DC Resistance)		—	—	0.1	Ω	≥ 600 Ohms @ 100MHz
REG_25	AVDD_L_EXT ⁽¹⁾	Ferrite Bead Current Rating		500	—	—	mA	—
REG_27	VDDOUT_LEXT^(2,3)	Buck Switch Mode Regulator Inductor Inductance (If LDO Mode not used)		8	10	12	µH	Shielded Inductor ONLY (If used in BUCK mode else No Connect)
REG_29		Inductor DCR (DC Resistance)		—	—	0.7	Ω	—
REG_31		Inductor ISAT Rating		275	—	—	mA	—
REG_33	BUCK_P_EFF	Buck Mode Power Efficiency		—	86	—	%	IOUT = 5mA
REG_35	BUCK_P_EFF	Buck Mode Power Efficiency		—	85	—	%	IOUT = 50mA
REG_36	VDDCORE	VDDCORE Voltage Range (PL0 mode)		—	0.9	—	V	CPU in Active or Idle Mode
REG_36	VDDCORE	VDDCORE Voltage Range (PL2 mode)		—	1.2	—	V	CPU in Active or Idle Mode
REG_36A	V_{SCALING_STEP}	VDDCORE / VDDPLL Voltage Scaling Step Size		—	5	—	mV	Step size for PL0 to PL2 (or PL2 to PL0) transition
REG_37	VDD⁽⁴⁾	VDD Input Voltage Range		1.62	3.3	3.63	V	PIC32CM LE00 / PIC32CM LS00
REG_37	VDD⁽⁴⁾	VDD Input Voltage Range		2.0	3.3	3.63	V	PIC32CM LS60
REG_38	VDDPLL	VDDPLL Voltage Range (PL0 mode)		—	0.9	—	V	CPU in Active or Idle Mode
REG_38	VDDPLL	VDDPLL Voltage Range (PL2 mode)		—	1.2	—	V	CPU in Active or Idle Mode
REG_39	AVDD⁽⁴⁾	AVDD Input Voltage Range		1.62	3.3	3.63	V	PIC32CM LE00 / PIC32CM LS00
REG_39	AVDD⁽⁴⁾	AVDD Input Voltage Range		2.0	3.3	3.63	V	PIC32CM LS60
REG_43	SVDD_R	VDD/AVDD Rise Ramp Rate to ensure internal Power-on Reset Signal		—	—	0.1	V/µs	Failure to meet this specification may lead to start-up or unexpected behaviors
REG_44	SVDD_F	VDD/AVDD Falling Ramp Rate to ensure internal Power-on Reset Signal		—	—	0.05	V/µs	Failure to meet this specification may cause the device to not detect reset
REG_45	VPOR	Power-on Reset		0.6	—	1.63	V	VDD/AVDD Power up/Down
REG_47	VBOD33 ^(6,7)	BOD33.VREFSEL=0		1.57	—	1.60	V	BOD33.LEVEL = 0x4 (Default Factory Value)
		BOD33.VREFSEL=0		3.60	—	3.68		BOD33.LEVEL = 0x3F
		BOD33.VREFSEL=1		1.64	—	1.79		BOD33.LEVEL = 0x11
		BOD33.VREFSEL=1		2.91	—	3.18		BOD33.LEVEL = 0x3F
REG_51	VBOD33_{LEVEL_STEP}	VBOD33 step size (BOD33.LEVEL)	BOD33.VREFSEL=0	—	34	—	mV	Step size
REG_51	VBOD33_{LEVEL_STEP}	VBOD33 step size (BOD33.LEVEL)	BOD33.VREFSEL=1	—	28	—	mV	Step size
REG_52	VBOD33_{HYST_STEP}	VBOD33 Hysteresis step size (BOD33.HYST)		—	Note ⁽⁷⁾	—	mV	Step size
REG_53	T_RST	External RESET valid active pulse width		1	—	—	µs	Minimum reset active time to guarantee CPU reset
Note: Ferrite Bead ISAT(min) ≥ (IDDANA(max) * 1.15). Buck Inductor ISAT(min) ≥ ((ICAPACITOR + IVDDCORE_MAX) * 1.2) when BUCK mode enabled. User must select either LDO or BUCK Mode. The modes are mutually exclusive. VDD and AVDD must be at the same voltage level. All bypass caps should be located immediately adjacent to pins and on the same side of the PCB as the MCU. Each primary power supply group VDD, AVDD, VDDCORE and VDDPLL should have one bulk capacitor and all power pins everywhere a 100nF bypass cap. Min and max represent absolute values including cap tolerances. VBOD33(min): BOD33.VREFSEL=0 => VBOD33(min) = 1.43 + (BOD33.LEVEL[5:0]) * 0.0344 BOD33.VREFSEL=1 => VBOD33(min) = 1.17 + (BOD33.LEVEL[5:0]) * 0.0276 VBOD33(max): (VBOD33(max)@BOD33.HYST=1) = (VBOD33(max)@BOD33.HYST=0) + VBOD33_{HYST_STEP} where VBOD33_{HYST_STEP} can be obtained for both BOD33.VREFSEL settings using the following graph: