1.2.23.4 ADC Clock

All ADC conversions operate at this frequency. Silicon requirements limit it to less than 10 Mhz. This has no relationship to the ACM Clock.

This clock is completely internal to the AB block. ASB sets this clock. The maximum ideal frequency for the ADC is based on the System Frequency entered in the ASB during Analog System configuration. This is based on the acquisition times entered for each peripheral.

There are a limited number of dividers available in the AB macro for this clock calculation, specifically 0, 4, 8, 12, 16, etc. This implies that certain System Clock settings result in faster ADC Clock frequencies. For example, a System Clock frequency of 40 Mhz enables a maximum possible 10 Mhz ADC Clock, whereas a 50 Mhz System Frequency results in a slower ADC Clock.