2.1.9.1 IP Cores for ADC Data Processing and Sequence Control With Calibration

This configuration enables the full Analog System feature set, including sequencing, flag generation, data averaging, general analog‑to‑digital converter (ADC) management, and calibration. This option allows you to or disable access to ADC results, ADC Status ASSC RAM, SMEV RAM, SMEV Status, ACM Bus, and ACM Clock.

When calibration is enabled, the analog block and the complete analog system controller are instantiated with calibration support, as shown in the following figure.