2.1.9.2 IP Cores for ADC Sequence control with calibration

This configuration instantiates only the analog block model and the analog sample sequence controller (ASSC) RAM, with calibration enabled. The data‑processing portions of the controller—the sample monitor and evaluation block (SMEV) and the sample monitor and threshold block (SMTR)—are omitted from the design, as shown in the following figure.

Figure 2-11. System Diagram for IP Cores for ADC Sequence Control Only

When this option is selected, you must process the analog‑to‑digital converter (ADC) data directly from the ADC result bus or from the ASSC RAM.