24.2.1 PTG Control/Status Low Register

Note:

These bits apply to the PTGWHI and PTGWLO commands only.
This bit is only used with the PTGCTRL Step command software trigger option.
The PTGSSEN bit may only be written when in Debug mode.

Name:	PTGCST
Offset:	0x900


Bit	15	14	13	12	11	10	9	8
	PTGEN		PTGSIDL	PTGTOGL		PTGSWT	PTGSSEN	PTGIVIS
Access	R/W		R/W	R/W		R/W	R/W	R/W
Reset	0		0	0		0	0	0


Bit	7	6	5	4	3	2	1	0
	PTGSTRT	PTGWDTO	PTGBUSY				PTGITM[1:0]
Access	R/W	R/W	R/W				R/W	R/W
Reset	0	0	0				0	0

Bit 15 – PTGEN PTG Broadcast Trigger Enable bit

Value	Description
`1`	PTG is enabled
`0`	PTG is disabled

Bit 13 – PTGSIDL PTG Freeze in Debug Mode bit

Value	Description
`1`	Halts PTG operation when device is Idle
`0`	PTG operation continues when device is Idle

Bit 12 – PTGTOGL PTG Toggle Trigger Output bit

Value	Description
`1`	Toggles state of TRIG output for each execution of `PTGTRIG`
`0`	Generates a single TRIG pulse for each execution of `PTGTRIG`

Bit 10 – PTGSWT PTG Software Trigger bit⁽²⁾

Value	Description
`1`	If the PTG state machine is executing the “Wait for software trigger” Step command (OPTION[3:0] = `1010` or `1011`), the command will complete and execution will continue
`0`	No action other than to clear the bit

Bit 9 – PTGSSEN PTG Single-Step Command bit⁽³⁾

Value	Description
`1`	Enables single Step when in Debug mode
`0`	Disables single Step

Bit 8 – PTGIVIS PTG Counter/Timer Visibility bit

Value	Description
`1`	Reading the PTGSDLIM, PTGCxLIM or PTGTxLIM register returns the current values of their corresponding Counter/Timer registers (PTGSDLIM, PTGCxLIM and PTGTxLIM)
`0`	Reading the PTGSDLIM, PTGCxLIM or PTGTxLIM register returns the value of these Limit registers

Bit 7 – PTGSTRT PTG Start Sequencer bit

Value	Description
`1`	Starts to sequentially execute the commands (Continuous mode)
`0`	Stops executing the commands

Bit 6 – PTGWDTO PTG Watchdog Timer Time-out Status bit

Value	Description
`1`	PTG Watchdog Timer has timed out
`0`	PTG Watchdog Timer has not timed out

Bit 5 – PTGBUSY PTG State Machine Busy bit

Value	Description
`1`	PTG is running on the selected clock source; no SFR writes are allowed to PTGCLK[2:0] or PTGDIV[4:0]
`0`	PTG state machine is not running

Bits 1:0 – PTGITM[1:0] PTG Input Trigger Operation Selection bits⁽¹⁾

Value	Description
`11`	Single-level detect with Step delay not executed on exit of command (regardless of the `PTGCTRL` command) (Mode 3)
`10`	Single-level detect with Step delay executed on exit of command (Mode 2)
01	Continuous edge detect with Step delay not executed on exit of command (regardless of the `PTGCTRL` command) (Mode 1)
00	Continuous edge detect with Step delay executed on exit of command (Mode 0)

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