24.2.2 PTG Control/Status Register

Name:	PTGCON
Offset:	0x902


Bit	15	14	13	12	11	10	9	8
	PTGCLK[2:0]			PTGDIV[4:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	PTGPWD[3:0]					PTGWDT[2:0]
Access	R/W	R/W	R/W	R/W		R/W	R/W	R/W
Reset	0	0	0	0		0	0	0

Bits 15:13 – PTGCLK[2:0] PTG Module Clock Source Selection bits

Value	Description
`111`	CLC1 output
`110`	F_VCO/4
`101`	Reserved
`100`	Reserved
`011`	Input from Timer1 Clock pin, T1CK
`010`	ADC clock
`001`	F_CY
`000`	F_P

Bits 12:8 – PTGDIV[4:0] PTG Module Clock Prescaler (Divider) bits

Value	Description
`11111`	Divide-by-32
`11110`	Divide-by-31
. . .
`00001`	Divide-by-2
`00000`	Divide-by-1

Bits 7:4 – PTGPWD[3:0] PTG Trigger Output Pulse-Width (in PTG clock cycles) bits

Value	Description
`1111`	All trigger outputs are 16 PTG clock cycles wide
`1110`	All trigger outputs are 15 PTG clock cycles wide
. . .
`0001`	All trigger outputs are 2 PTG clock cycles wide
`0000`	All trigger outputs are 1 PTG clock cycle wide

Bits 2:0 – PTGWDT[2:0] PTG Watchdog Timer Time-out Selection bits

Value	Description
`111`	Watchdog Timer will time out after 512 PTG clocks
`110`	Watchdog Timer will time out after 256 PTG clocks
`101`	Watchdog Timer will time out after 128 PTG clocks
`100`	Watchdog Timer will time out after 64 PTG clocks
`011`	Watchdog Timer will time out after 32 PTG clocks
`010`	Watchdog Timer will time out after 16 PTG clocks
`001`	Watchdog Timer will time out after 8 PTG clocks
`000`	Watchdog Timer is disabled

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