24.2.10 PTG Counter 1 Limit Register
Note:
- These bits are read-only when the module is executing Step commands.
| Name: | PTGC1LIM(1) |
| Offset: | 0x91C |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PTGC1LIM[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PTGC1LIM[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 15:0 – PTGC1LIM[15:0] PTG Counter 1 Limit Register bits
This register is used to specify the loop count for the PTGJMPC1
Step command or as a Limit register for the General Purpose Counter 1.