24.2.8 PTG Step Delay Limit Register
Note:
- These bits are read-only when the module is executing Step commands.
| Name: | PTGSDLIM(1) |
| Offset: | 0x914 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PTGSDLIM[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PTGSDLIM[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 15:0 – PTGSDLIM[15:0] PTG Step Delay Limit Register bits
This register holds a PTG Step delay value representing the number of additional PTG clocks between the start of a Step command and the completion of a Step command.