3.5.29 Y Page Register
| Name: | YPAG |
| Offset: | 0x56 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| YPAG[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 7:0 – YPAG[7:0] Y Page bits
Note: When implemented, YPAG is a R/W SFR
register which resets to 0x0001. When not implemented, YPAG is a read-only SFR
register which will always return the fixed Y RAM page value, 0x0001.