3.5.30 EDS Bus Initiator Priority Control Register
| Name: | MSTRPR |
| Offset: | 0x58 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DMAPR | CANPR | CAN2PR | NVMPR | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 5 – DMAPR Modify DMA Controller Bus Initiator Priority Relative to CPU bit
| Value | Description |
|---|---|
| 1 | Raises DMA Controller bus Initiator priority to above that of the CPU |
| 0 | No change to DMA Controller bus Initiator priority |
Bit 4 – CANPR Modify CAN1 Bus Initiator Priority Relative to CPU bit
| Value | Description |
|---|---|
| 1 | Raises CAN1 bus Initiator priority to above that of the CPU |
| 0 | No change to CAN1 bus Initiator priority |
Bit 3 – CAN2PR Modify CAN2 Bus Initiator Priority Relative to CPU bit
| Value | Description |
|---|---|
| 1 | Raises CAN2 bus Initiator priority to above that of the CPU |
| 0 | No change to CAN2 bus Initiator priority |
Bit 0 – NVMPR Modify NVM Controller Bus Initiator Priority Relative to CPU bit
| Value | Description |
|---|---|
| 1 | Raises NVM Controller bus Initiator priority to above that of the CPU |
| 0 | No change to NVM Controller bus Initiator priority |