3.5.20 Core Control Register

Note:

This bit is always read as ‘0’.
The IPL3 bit is concatenated with the IPL[2:0] bits (SR[7:5]) to form the CPU Interrupt Priority Level.

Legend: C = Clearable bit

Name:	CORCON
Offset:	0x44


Bit	15	14	13	12	11	10	9	8
	VAR		US[1:0]		EDT	DL[2:0]
Access	R/W		R/W	R/W	R/W	R	R	R
Reset	0		0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	SATA	SATB	SATDW	ACCSAT	IPL3	SFA	RND	IF
Access	R/W	R/W	R/W	R/W	R/C	R	R/W	R/W
Reset	0	0	1	0	0	0	0	0

Bit 15 – VAR Variable Exception Processing Latency Control bit

Value	Description
`1`	Variable exception processing is enabled
`0`	Fixed exception processing is enabled

Bits 13:12 – US[1:0] DSP Multiply Unsigned/Signed Control bits

Value	Description
`11`	Reserved
`10`	DSP engine multiplies are mixed sign
`01`	DSP engine multiplies are unsigned
`00`	DSP engine multiplies are signed

Bit 11 – EDT Early `DO` Loop Termination Control bit⁽¹⁾

Value	Description
`1`	Terminates executing `DO` loop at the end of the current loop iteration
`0`	No effect

Bits 10:8 – DL[2:0] `DO` Loop Nesting Level Status bits

Value	Description
`111`	7 `DO` loops are active
`. . .`
`001`	1 `DO` loop is active
`000`	0 `DO` loops are active

Bit 7 – SATA ACCA Saturation Enable bit

Value	Description
`1`	Accumulator A saturation is enabled
`0`	Accumulator A saturation is disabled

Bit 6 – SATB ACCB Saturation Enable bit

Value	Description
`1`	Accumulator B saturation is enabled
`0`	Accumulator B saturation is disabled

Bit 5 – SATDW Data Space Write from DSP Engine Saturation Enable bit

Value	Description
`1`	Data Space write saturation is enabled
`0`	Data Space write saturation is disabled

Bit 4 – ACCSAT Accumulator Saturation Mode Select bit

Value	Description
`1`	9.31 saturation (super saturation)
`0`	1.31 saturation (normal saturation)

Bit 3 – IPL3 CPU Interrupt Priority Level Status bit 3⁽²⁾

Value	Description
`1`	CPU Interrupt Priority Level is greater than 7
`0`	CPU Interrupt Priority Level is 7 or less

Bit 2 – SFA Stack Frame Active Status bit

Value	Description
`1`	Stack frame is active; W14 and W15 address 0x0000 to 0xFFFF, regardless of DSRPAG
`0`	Stack frame is not active; W14 and W15 address the base Data Space

Bit 1 – RND Rounding Mode Select bit

Value	Description
`1`	Biased (conventional) rounding is enabled
`0`	Unbiased (convergent) rounding is enabled

Bit 0 – IF Integer or Fractional Multiplier Mode Select bit

Value	Description
`1`	Integer mode is enabled for DSP multiply
`0`	Fractional mode is enabled for DSP multiply

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