9.2.2.2 Output Enable for PORTx Register
| Name: | TRISx |
| Offset: | 0xE02, 0xE1E, 0xE34, 0xE56, 0xE72 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TRISx[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TRISx[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
Bits 15:0 – TRISx[15:0] Output Enable for PORTx bits
| Value | Description |
|---|---|
1 |
LATx[n] is not driven on the PORTx[n] pin |
0 |
LATx[n] is driven on the PORTx[n] pin |