5.15.11.4 System Interrupt Register 2
| Name: | SIR2 |
| Offset: | 0x14 |
| Reset: | 0x0 |
| Property: | R/W |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Reserved | VDD2OV | VDD1OV | VDD2UV | VDD1UVH | VDD1UVL | Reserved[1:0] | |||
| Access | R | R/W | R/W | R/W | R/W | R/W | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – Reserved
(Submit Feedback)Reserved, do not modify reset value!
Bit 6 – VDD2OV
(Submit Feedback)| Value | Description |
|---|---|
| 1 | An overvoltage event has been detected at the VDD2 pin AND the VDD2OVECE bit set to ‘1’. |
| 0 | The bit is reset to ‘0’ by writing a ‘1’ to it. |
Bit 5 – VDD1OV
(Submit Feedback)| Value | Description |
|---|---|
| 1 | An overvoltage event has been detected at the VDD1 pin AND the VDD1OVECE bit set to ‘1’. |
| 0 | The bit is reset to ‘0’ by writing a ‘1’ to it. |
Bit 4 – VDD2UV
(Submit Feedback)| Value | Description |
|---|---|
| 1 | An undervoltage event has been detected at the VDD2 pin AND the VDD2UVECE bit set to ‘1’. |
| 0 | The bit is reset to ‘0’ by writing a ‘1’ to it. |
Bit 3 – VDD1UVH
(Submit Feedback)| Value | Description |
|---|---|
| 1 | An undervoltage event has been detected at the VDD1 pin AND the VDD1UVHECE bit set to ‘1’. |
| 0 | The bit is reset to ‘0’ by writing a ‘1’ to it. |
Bit 2 – VDD1UVL
(Submit Feedback)| Value | Description |
|---|---|
| 1 | An undervoltage event has been detected at the VDD1 pin AND the VDD1UVLECE bit set to ‘1’. |
| 0 | The bit is reset to ‘0’ by writing a ‘1’ to it. |
Bits 1:0 – Reserved[1:0]
(Submit Feedback)Reserved, do not modify reset value!
