5.15.11.8 Device Status Register 1
| Name: | DSR1 |
| Offset: | 0x10 |
| Reset: | 0x0 |
| Property: | R |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SMTS | VDD2OTPWS | VDD1OTPWS | GDUOTPWS | LOTPWS | GDUS | LTXDOUTS | LTXS | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – SMTS
(Submit Feedback)| Value | Description |
|---|---|
| 1 | The prior transition to Sleep mode was forced by a VIO overvoltage event. |
| 0 | The prior transition to Sleep mode was triggered by an SPI command. |
Bit 6 – VDD2OTPWS
(Submit Feedback)| Value | Description |
|---|---|
| 1 | The junction temperature of the VDD2 regulator exceeds the overtemperature prewarning level (TOT_PREW_Set). |
| 0 | The bit is reset to ‘0’ as soon as the junction temperature drops below the overtemperature prewarning clear level (TOT_PREW_Clear). |
Bit 5 – VDD1OTPWS
(Submit Feedback)| Value | Description |
|---|---|
| 1 | The junction temperature of the VDD1 regulator exceeds the overtemperature pre-warning level (TOT_PREW_Set). |
| 0 | The bit is reset to ‘0’ as soon as the junction temperature drops below the overtemperature pre-warning clear level (TOT_PREW_Clear). |
Bit 4 – GDUOTPWS
(Submit Feedback)| Value | Description |
|---|---|
| 1 | The junction temperature of the GDU exceeds the overtemperature pre-warning level (TOT_PREW_Set). |
| 0 | The bit is reset to ‘0’ as soon as the junction temperature drops below the overtemperature pre-warning clear level (TOT_PREW_Clear). |
Bit 3 – LOTPWS
(Submit Feedback)| Value | Description |
|---|---|
| 1 | The junction temperature of the LIN transceiver exceeds the overtemperature pre-warning level (TOT_PREW_Set). |
| 0 | The bit is reset to ‘0’ as soon as the junction temperature drops below the overtemperature pre-warning clear level (TOT_PREW_Clear). |
Bit 2 – GDUS
(Submit Feedback)| Value | Description |
|---|---|
| 1 | Set to ‘1’ as soon as the GDU is ready to drive the gate of the external MOSFETs. |
| 0 | Indicates the GDU is not ready yet to drive the gate of the external MOSFETs. |
Bit 1 – LTXDOUTS
(Submit Feedback)| Value | Description |
|---|---|
| 1 | The LIN transceiver is disabled due to a TXD dominant timeout event. |
| 0 | Indicates no TXD dominant timeout event is present. |
Bit 0 – LTXS
(Submit Feedback)| Value | Description |
|---|---|
| 1 | The LIN transceiver is ready to transmit and receive data. |
| 0 | Indicates no TXD the LIN transceiver is not ready yet to transmit and receive data. |