5.15.11.1 System Interrupt Event Capture Enable Register 1
| Name: | SIECER1 |
| Offset: | 0x18 |
| Reset: | 0xE7 |
| Property: | R/W |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| GSCECE | VDHOVECE | ILIMECE | Reserved[4:3] | VSUVECE | SPIFECE | OVTPWECE | |||
| Access | R/W | R/W | R/W | R | R | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | |
Bit 7 – GSCECE
(Submit Feedback)Bit 6 – VDHOVECE
(Submit Feedback)| Value | Description |
|---|---|
| 1 | Enables VDH overvoltage event capture |
| 0 | Disables VDH overvoltage event capture |
Bit 5 – ILIMECE
(Submit Feedback)| Value | Description |
|---|---|
| 1 | Enables current limitation event capture |
| 0 | Disables current limitation event capture |
Bits 4:3 – Reserved[4:3]
(Submit Feedback)Reserved, do not modify reset value!
Bit 2 – VSUVECE
(Submit Feedback)| Value | Description |
|---|---|
| 1 | Enables VS undervoltage event capture |
| 0 | Disables VS undervoltage event capture |
Bit 1 – SPIFECE
(Submit Feedback)| Value | Description |
|---|---|
| 1 | Enables SPI failure interrupt |
| 0 | Disables SPI failure interrupt |
Bit 0 – OVTPWECE
(Submit Feedback)| Value | Description |
|---|---|
| 1 | Enables overtemperature pre-warning event capture |
| 0 | Disables overtemperature pre-warning event capture |