5.15.11.7 System Interrupt Register 5
| Name: | SIR5 |
| Offset: | 0x17 |
| Reset: | 0x04 |
| Property: | R/W |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| VDHOV | VSUV | LOCWU | LINWU | SPIF | PWRON | SYSERR | OSCF | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
Bit 7 – VDHOV
(Submit Feedback)| Value | Description |
|---|---|
| 1 | The bit is set to ‘1’ if a VDH overvoltage event occurs AND the VDHOVECE bit is set to ‘1’. |
| 0 | The bit is reset to ‘0’ by writing a ‘1’ to it. |
Bit 6 – VSUV
(Submit Feedback)| Value | Description |
|---|---|
| 1 | The bit is set to ‘1’ if VS drops below the threshold VVS_UV_Set for longer than the fault blanking time AND the VSUVECE bit is set to ‘1’. |
| 0 | The bit is reset to ‘0’ by writing a ‘1’ to it. |
Bit 5 – LOCWU
(Submit Feedback)| Value | Description |
|---|---|
| 1 | The bit is set to ‘1’ if a local wake-up event occurs AND the local wake-up detection is enabled. |
| 0 | The bit is reset to ‘0’ by writing a ‘1’ to it. |
Bit 4 – LINWU
(Submit Feedback)| Value | Description |
|---|---|
| 1 | The bit is set to ‘1’ if a LIN wake-up event occurs AND the LIN bus wake-up detection is enabled. |
| 0 | The bit is reset to ‘0’ by writing a ‘1’ to it. |
Bit 3 – SPIF
(Submit Feedback)| Value | Description |
|---|---|
| 1 | The bit is set to ‘1’ if an SPI failure has been detected AND the SPIFECE bit is set to ‘1’. |
| 0 | The bit is reset to ‘0’ by writing a ‘1’ to it. |
Bit 2 – PWRON
(Submit Feedback)| Value | Description |
|---|---|
| 1 | The bit is set to ‘1’ if the device is no longer in the Power OFF mode. |
| 0 | The bit is reset to ‘0’ by writing a ‘1’ to it. |
Bit 1 – SYSERR
(Submit Feedback)| Value | Description |
|---|---|
| 1 | The bit
is set to ‘1’ in the following cases:
|
| 0 | The bit is not latched and will automatically reset to ‘0’ if the fault is no longer present. |
Bit 0 – OSCF
(Submit Feedback)| Value | Description |
|---|---|
| 1 | The bit is set to ‘1’ if the system clock is missing. No interrupt at the NIRQ pin will be generated without an internal system clock. The bit can, however, be read via SPI. |
| 0 | The bit is not latched and will automatically reset to ‘0’ as soon as the internal system clock recovers. |