5.15.11.2 System Interrupt Event Capture Enable Register 2
| Name: | SIECER2 |
| Offset: | 0x19 |
| Reset: | 0x1F |
| Property: | R/W |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Reserved[7:5] | VDD2UVECE | VDD1UVHECE | VDD1UVLECE | VDD2OVECE | VDD1OVECE | ||||
| Access | R | R | R | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | |
Bits 7:5 – Reserved[7:5]
(Submit Feedback)Reserved, do not modify reset value!
Bit 4 – VDD2UVECE
(Submit Feedback)| Value | Description |
|---|---|
| 1 | Enables VDD2 undervoltage event capture |
| 0 | Disables VDD2 undervoltage event capture |
Bit 3 – VDD1UVHECE
(Submit Feedback)| Value | Description |
|---|---|
| 1 | Enables VDD1 undervoltage event capture |
| 0 | Disables VDD1 undervoltage event capture |
Bit 2 – VDD1UVLECE
(Submit Feedback)| Value | Description |
|---|---|
| 1 | Enables VDD1 IO undervoltage event capture |
| 0 | Disables VDD1 IO undervoltage event capture |
Bit 1 – VDD2OVECE
(Submit Feedback)| Value | Description |
|---|---|
| 1 | Enables VDD2 overvoltage event capture |
| 0 | Disables VDD2 overvoltage event capture |
Bit 0 – VDD1OVECE
(Submit Feedback)| Value | Description |
|---|---|
| 1 | Enables VDD1 overvoltage event capture |
| 0 | Disables VDD1 overvoltage event capture |