11.2.41 CAN Transmitter Delay Compensation Register Low

Note:

These bits can only be modified in Configuration mode (OPMOD[2:0] = 100).
T_CAN = 1/F_CAN. F_CAN is the clock which comes out of the CAN clock generator.

Name:	C1TDCL
Offset:	0x6CC


Bit	15	14	13	12	11	10	9	8
		TDCO[6:0]
Access		R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset		0	0	1	0	0	0	0


Bit	7	6	5	4	3	2	1	0
			TDCV[5:0]
Access			R/W	R/W	R/W	R/W	R/W	R/W
Reset			0	0	0	0	0	0

Bits 14:8 – TDCO[6:0] Transmitter Delay Compensation Offset bits (Secondary Sample Point (SSP)^(1,2)

Value	Description
`111 1111`	-64 x T_CAN
. . .
`011 1111`	63 x T_CAN
. . .
`000 0000`	0 x T_CAN

Bits 5:0 – TDCV[5:0] Transmitter Delay Compensation Value bits (Secondary Sample Point (SSP)^(1,2)

Value	Description
`11 1111`	63 x T_SYSCLK
. . .
`00 0000`	0 x T_SYSCLK

DS70005452D

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