11.2.55 CAN Receive Overflow Interrupt Status Register Low

Note:

CxRXOVIFL: FIFO: RFOVIFx (flag needs to be cleared in the FIFO register).

Name:	CxRXOVIFL
Offset:	0x5A8, 0x6E8


Bit	15	14	13	12	11	10	9	8
	RFOVIF[15:8]
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	RFOVIF[7:1]
Access	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0

Bits 15:8 – RFOVIF[15:8] Unimplemented⁽¹⁾

Bits 7:1 – RFOVIF[7:1] Receive FIFO Overflow Interrupt Pending bits⁽¹⁾

Value	Description
`1`	Interrupt is pending
`0`	Interrupt is not pending

DS70005452D

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.