46.4 Supply Voltage

Table 46-3. Supply Voltage
SymbolMin.Typ. ✝Max.UnitsConditions
Supply Voltage(1)
VDD2.7-5.5V
VDDIO21.71-5.5V
VDD Slew Rate--0.25V/µs
RAM Data Retention(2)
VDR1.7--VDevice in Power-Down mode
Power-on Reset Release Voltage(4)
VPOR-1.61.8VBOD disabled(3)
tPOR-1-µsBOD disabled(3)
Power-on Reset Re-Arm Voltage(4)
VPORR 1.3-VBOD disabled(3)
tPORR-2.7-µsBOD disabled(3)
VDD Rise Rate to Ensure Internal Power-on Reset Signal(4)
SVDD *0.05--V/msBOD disabled(3)

✝ Unless otherwise specified, data in the “Typ.” column is at TA = 25°C and VDD = 3.0V. These parameters are not tested and are for design guidance only.

* These parameters are characterized but not tested in production.

Note:
  1. During Chip Erase, the Brown-out Detector (BOD) configured with BODLEVEL0 is forced ON. If the supply voltage VDD is below VBOD for BODLEVEL0, the erase attempt will fail.
  2. This is the limit to which VDD can be lowered in sleep mode without losing RAM data.
  3. Refer to the RSTCTRL section for BOD trip point information.
  4. Refer to the POR and PORR with Slow-Rising VDD figure below.
Figure 46-1. POR and PORR with Slow-Rising VDD
Note:
  • The device is held in Reset when POR is low