46.7 I/O Pins

Table 46-6. I/O Pin Specifications(1)
SymbolDescriptionMin.Typ. ✝Max. 85°CUnitsConditions
Input Low Voltage
VILI/O PORT:
• With Schmitt Trigger buffer--0.2×VDDVPINnCTRL.INLVL = 0x00
• With LVBUF (TTL compatible)--0.8VPINnCTRL.INLVL = 0x01
RESET Pin--0.2×VDDV
Input High Voltage
VIHI/O PORT:
• With Schmitt Trigger buffer0.8×VDD--VPINnCTRL.INLVL = 0x00
• With LVBUF (TTL compatible)2--VPINnCTRL.INLVL = 0x01
RESET Pin0.8×VDD--V
Input Leakage Currents(2)
IILI/O PORTS(3)-±5±125nAGND ≤ VPIN ≤ VDD, pin at high-impedance, TA= 85°C
-±5±1000nAGND ≤ VPIN ≤ VDD, pin at high-impedance, TA= 125°C
RESET Pin(4) *-±50±200nAGND ≤ VPIN ≤ VDD, pin at high-impedance, TA= 85°C
Pull-up Current
IPUR 90150200µAVDD = 3.0V, VPIN = GND
Output Low Voltage
VOL --0.6VIOL = 10 mA, VDD = 3.0V
Output High Voltage
VOH VDD - 0.7--VIOH = 6 mA, VDD = 3.0V
I/O Slew Rate*
Rising slew rate-22-nsPORTCTRL.SRL = 0x00
-45-nsPORTCTRL.SRL = 0x01
Falling slew rate-16-nsPORTCTRL.SRL = 0x00
-30-nsPORTCTRL.SRL = 0x01
Pin Capacitance*
CIOVREF pin-7-pF
XTAL pins-4-pF
Other pins-4-pF

✝ Unless otherwise specified, data in the “Typ.” column is at TA = 25°C and VDD = 3.0V. These parameters are not tested and are for design guidance only.

* These parameters are characterized but not tested in production.

Note:
  1. These figures are valid for all I/O ports regardless of whether they are connected to the VDD or VDDIO2 power domain.
  2. The negative current is defined as the current sourced by the pin.
  3. The leakage current numbers for I/O PORTS are also valid when the pin is used as input to an enabled analog peripheral.
  4. The leakage current on the RESET pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. A higher leakage current may be measured at different input voltages.
  5. The input voltage threshold is relative to VDDIO2 on MVIO pins (PORTC) and VDD on other pins.