46.17 TWI

Figure 46-7. TWI - Timing Requirements

Table 46-23. TWI - Timing Characteristics
Symbol	Description	Min.	Typ. ✝	Max.	Units	Conditions
f_SCL	SCL clock frequency⁽¹⁾	—	—	1000	kHz	Fm+
		—	—	400	kHz	Fm
		—	—	100	kHz	Sm
V_IL	LOW-level input voltage	-0.5	—	0.3×V_DD	V	INPUTLVL=0x0 (I²C)
V_IL	LOW-level input voltage	-0.5	—	0.8	V	INPUTLVL=0x1 (SMBUS)
V_IH	HIGH-level input voltage⁽²⁾	0.7×V_DD	—	V_DD+0.5V	V	INPUTLVL=0x0 (I²C)
V_IH	HIGH-level input voltage⁽²⁾	1.35	—	V_DD+0.5V	V	INPUTLVL=0x1 (SMBUS)
V_HYS*	Hysteresis of Schmitt Trigger inputs	0.05×V_DD	—	—	V	INPUTLVL=0x0 (I²C)
V_HYS*	Hysteresis of Schmitt Trigger inputs	—	0.2	—	V	INPUTLVL=0x1 (SMBUS)
V_OL	Output low voltage⁽³⁾	—	—	0.6	V	I_LOAD = 6 mA
t_SP *	Spikes suppressed by the input filter	0	—	t_SPM	ns
t_SPM *	Input filter delay	50	—	200	ns
t_{HD_DAT} *	Data hold time	—	0	—	ns	SDAHOLD[1:0] = 0x0 (for most applications)
		—	50	—		SDAHOLD[1:0] = 0x1
		—	300	—		SDAHOLD[1:0] = 0x2
		300	500	900		SDAHOLD[1:0] = 0x3 (for SMBus 2.0)
✝Unless otherwise specified, data in the “Typ.” column is at T_A = 25°C and V_DD = 3.0V. These parameters are not tested and are for design guidance only. * These parameters are not tested and are for design guidance only. Note: The system clock frequency must be at least 10 times faster than the TWI bus clock (f_{CLK_PER} ≥ 10×f_SCL), but additional limitations may apply depending on the baud rate. Refer to the TWI section for more detailed information. If a TWI pin is above V_DD+0.5V, current will flow from the TWI pin to V_DD. I²C Fm+ full 20 mA drive capability is not supported.