15.4.3.5.6 Software PCI Control
All PCI blocks have provisions for software control to force and clear events or for development debugging. There are three controls that can be used to manually control the PCI inputs:
- SWPCI Control Bit
- SWPCIM Demultiplexer (for SWPCI Control Bit)
- SWTERM to Generate a Termination Event
The SWPCI control bit (PGxyPCI1[23]) can have its programmed state
of ‘0’ or ‘1’ routed to one of three destinations, specified by the SWPCIM[1:0] bits
(PGxyPCI1[22:21]), as shown in Figure 15-24.
The SWTERM bit is tied directly to the terminator event input
logic, and it can be used to manually terminate PCI events by writing a ‘1’ to SWTERM and having the TERM[2:0] bits selection
set to ‘000’. Additionally, the acceptance and
terminator qualifier input multiplexers have an option to output a fixed state of
‘1’ or, when used with their respective
polarity control, a fixed state of ‘0’. These
fixed states can be used for debugging or when the acceptance function is not
needed.
PCI Source EOC, Level Mode
When the PCI acceptance logic is operated in Level mode and the PCI source is synchronized to the EOC event, there is no logic that retains the state of the prior PCI source signal. Therefore, the resultant PCI output is simply the PCI source signal synchronized to the EOC event. This configuration is useful for PWM chopping applications where the PCI source signal is used as a gating signal. The gating signal is automatically aligned to the PWM cycle boundaries, as shown in Figure 15-25.
PCI Source EOC, Edge Modes
When the PCI acceptance logic is operated in the Rising Edge or
Any Edge modes and PSYNC = 1, the PCI source is
synchronized to the EOC event, as shown in Figure 15-26. If an edge event is detected, the pulse is delayed until the next EOC event. In the
case that a PCI source signal becomes active and then inactive within a single PWM
cycle, the PCI active signal will not assert.
PCI Source EOC, Latched Modes
When the PCI acceptance logic is operated in the Latched mode and
PSYNC = 1, the PCI source is synchronized to the
EOC event, as shown in Figure 15-27. The
synchronization logic delays the rising edge of the PCI source signal until the next
occurrence of the EOC signal. The output of the synchronization logic is deasserted on
the falling edge of the PCI source signal. The output of the synchronization logic is
then used to set the SR latch. A PCI input pulse that operates entirely within one EOC
period will not assert the PCI active signal. This is because the falling edge of the
PCI input signal resets the EOC synchronization logic before an event can be
produced.
PCI Source EOC, Latched Edge Modes
When the PCI acceptance logic is operated in the Latched Edge
modes and PSYNC = 1, the PCI source is
synchronized to the EOC event, as shown in Figure 15-28. This configuration operates similar to the Rising Edge and Any Edge modes, except
that the event output of the synchronization logic is latched. A PCI source input pulse
that operates entirely within a PWM cycle will assert the PCI active signal.
PCI Terminator EOC
By default, the PCI logic synchronizes a terminator event to the PWM EOC. This allows the PWM to resume cleanly at the start of a new cycle. The rising edge of the terminating signal is held off until an occurrence of the EOC event. The terminator signal is usually a pulse event used to reset the latched state of the PCI logic. If a short pulse is received prior to the occurrence of an EOC event, a Reset pulse is produced at the next EOC event. If the terminator signal is a longer pulse, the synchronized output is held active for as long as the terminator signal is present. This behavior can be used to force the PCI logic to a Reset state, if desired. Terminator event synchronization timing is shown in Figure 15-29.