15.4.3.5.3 PCI Logic Description

The PCI block contains three major blocks to support a wide range of applications. First are the inputs, with logic for selecting and conditioning the input signals. Second is the PCI acceptance logic, which is the selectable logic functions applied to the inputs, and finally, there is the output logic, including bypass.

PCI Source

The PCI source input is the main input into the PCI block and has the following features:

  • Input Selection Multiplexer
  • Polarity Control
  • Software Control (SW override)
  • Edge Detect Circuit for Auto-Terminate
  • End-of-Cycle (EOC) Synchronization

The PCI source is selected using the PSS[31:0] control bits (PGxyPCI2[31:0]). The polarity of the PCI input source can be selected using the PPS control bit. The chosen PCI input source may be optionally synchronized to the end of a PWM cycle using the PSYNC control bit. This synchronization is useful when a PCI signal is used to gate PWM pulses, as the PCI signal can be delayed to the next PWM boundary, ensuring that a partial pulse is not produced at the output. A falling edge detect circuit is present and can be used to automatically terminate the PCI active signal when selected by the terminator event selection multiplexer.

PCI Source Qualifier

The PCI source qualifier is a second input signal used to ‘qualify’ the PCI source. The PCI source qualifier is ANDed with the PCI source within the PCI acceptance logic. Inputs into the PCI source qualifier multiplexer include:

  • Duty Cycle Active
  • LEB Active
  • PWM Generator Triggered
  • PWMx Output Selected by PWMPCI[2:0] (PGxEVT1[23:21])
  • External Input (Another Peripheral or Device Pin)

Like the PCI source input, the PCI source qualifier input has polarity and software control. The PCI source qualifier is used in all PCU acceptance logic types; however, if it is unneeded, AQSS[2:0] (PGxyPCI1[10:8]) can be set to ‘000’ to effectively disable the qualifier.

PCI Terminator Event and Qualifier

The PCI termination event sources are used only in the Latched modes of the PCI acceptance logic functions and are used to reset the latch. Inputs to the terminator event inputs include:

  • SWTERM Bit
  • Trigger Events (Trigger A, B, C)
  • Auto-Termination (Falling Edge Detect on PCI Source)
  • PWMx Output Selected by PWMPCI[2:0] (PGxEVT1[23:21])
  • External Input (Another Peripheral or Device Pin)

The default option for the PCI terminator is SWTERM. The SWTERM bit must be written at least two PGx_clk cycles prior to the EOC. Otherwise, the PCI termination event will be delayed until the following EOC. The PCI trigger option (Trigger A, B or C) allows the PCI logic to be reset at a particular time in the PWM cycle. User software must select the appropriate PGxTRIG to be used as the PCI trigger source. When using Automatic Termination mode, it is recommended to select ‘none’ as the PCI termination qualifier. An EOC synchronization is provided by default and can be disabled by setting the TSYNCDIS bit (PGxyPCI1[15]).

The inputs and features of the termination qualifier are similar to the PCI source qualifier. The termination qualifier is used to create more advanced termination events.

Using a PWMx Output for PCI Function Input

The PWMPCI[2:0] control bits (PGxEVT1[23:21]) are used to select which one of the eight PWM outputs can be used by the PCI block. In some control loops, it is desirable to use the output of one PWM Generator to control another generator. The selected PWMx output is made available as a selection on the PCI source qualifier select, PCI terminator event select and PCI termination qualifier select MUXes, as shown in Figure 15-22.

Figure 15-22. PWM Source Selection for PCI