16.4.5 Triggers

The channel trigger source is defined in the ADnCHxCON1 register. The trigger source is selected by the TRG1SRC[5:0] and TRG2SRC[5:0] bits.

TRG1SRC[4:0] bits:

  • Define a trigger source for a single conversion mode (MODE[1:0] bits = ‘00’).
  • Select a signal to enable/gate the TRG2SRC[5:0] triggers in the Window mode (MODE[1:0] bits = ‘01’). The polarity of the TRG1SRC[5:0] signal can be changed by TRG1POL bit.
  • Define the start/first trigger source for Integration and Oversampling modes (MODE[1:0] bits = ‘10’ and MODE[1:0] bits = ‘11’).

TRG2SRC[5:0] bits:

  • Are not used for a Single Conversion mode (MODE[1:0] bits = ‘00’).
  • Select a trigger source for all conversions in the Window mode (MODE[1:0] bits = ‘01’).
  • Re-trigger ADC in Integration and Oversampling modes after the first trigger specified by TRG1SRC[5:0] bits (MODE[1:0] bits = ‘10’ and MODE[1:0] bits = ‘11’).

The following types of triggers are available:

  • Software
  • Back-to-back
  • Repeat timer
  • From other peripheral modules

Software Trigger

The software trigger is used when TRG1SRC[5:0] or TRG2SRC[5:0] bits are set to ‘00001’. Trigger is generated when the corresponding bit in the ADnSWTRG register is set.

Back-to-Back Trigger

The channel is re-triggered immediately after the previous conversion is finished when TRG1SRC[5:0] or TRG2SRC[5:0] bits are set to ‘00010’. The channel conversions are executed back-to-back. The timing is affected (can be delayed) by priorities of other channels.

Repeat Timer Trigger

The channel is triggered from an internal ADC repeat timer when TRG1SRC[5:0] or TRG2SRC[5:0] bits are set to ‘00011’. This timer is clocked from the ADC analog core clock (TAD), and its period is set by RPTCNT[5:0] bits.

Peripheral Modules Triggers

All other TRG1SRC[5:0] and TRG2SRC[5:0] bit settings starting from ‘00100’ select trigger sources from other modules. These trigger options are device specific.