16.4.7 Comparator

Each ADC channel has a dedicated digital comparator that compares each conversion result from ADnRESx register or the channel data from ADnDATAx register with thresholds stored in the ADnCMPLOx and ADnCMPHIx registers. The comparator source selection between ADnRESx and ADnDATAx registers is controlled by CMPVAL bit (ADnCHxCON2[29]). When CMVAL bit is zero, the ADmRESx register is used, and when CMPVAL bit is set, the ADnDATAX register is selected for the comparator operation. The following comparison criteria can be set by the CMPMOD[2:0] bits (ADnCHxCON2[14:12]):

Each channel can be programmed to generate the comparator interrupt upon a set number of the criteria match events. The number of the match events is set by ADCMPCNT[9:0] bits (ADnCHxCON2[9:0]). The ADCMPSTAT[9:0] bits (ADnCHxCON2[25:16]) hold the current number the match events occurred. The comparator can count consecutive or accumulative match events. This is selected by CMPMODE bit (ADnCHxCON2[28]). If the CMPMODE bit is zero, then the comparator will generate an event only when a number of consecutive match events is detected. If the CMPMODE bit is set, then the comparator will accumulate/count the match events and generate the interrupt when the event number will exceed the number programmed in ADCMPCNT[9:0] bits. When the comparison match event is detected, the corresponding channel CMPxFLG bit in ADnCMPSTAT register and the ADnCMPxIF interrupt flag are set.