16.4.8 Interrupts
Each channel has an individual result ready interrupt with a ADnCHxIF flag in the
corresponding IFC register. The channel interrupt can be enabled by setting the ADnCHxIE
bit in the IEC register. There are two Interrupt modes defined by the IRQSEL bit
(ADnCHxCON1[21]). If the IRQSEL bit is zero, the channel interrupt is generated after
each single conversion when result is ready in the ADnRESx register. If the IRQSEL bit
is set, the channel interrupt is generated when data are ready in the ADnDATAx register.
For the IRQSEL bit = 1 option, the channel interrupt is generated:
- After each conversion for the Single Conversion mode (MODE[1:0] bits = ‘00’)
- For the Window mode (MODE[1:0] bits = `01'), when the number of conversions reaches a value in CNTx[15:0] bits (ADnCNTx[15:0]) or when the gate signal defined by TRG1SRC[5:0] bits is de-asserted.
- When all conversions are finished for the Oversampling or Integration modes (MODE[1:0] bits = ‘10’ or ‘11’).