16.4.10 Result
The result of each single conversion is stored in the ADnRESx register. For the Multiple
Conversion modes (MODE[1:0] != ‘00’), the results are added to a
primary accumulator (ADnDATAx). The result sum in ADnDATAx register is valid only when
the corresponding CHxRDY bit is set in ADnSTAT register.
The result value is formatted using DIFF and FRAC bit settings (ADnCHxCON1[31] and ADnCHxCON1[30]). The format options are explained in Table 16-5.
| Differential Format Option DIFF bit | Input Voltage | Conversion Result | |||
|---|---|---|---|---|---|
| (VINP = Voltage on non-inverting input, VINN = Voltage on inverting input) | FRAC bit = 0 | FRAC bit = 1 | |||
| Decimal | Hex | Decimal | Hex | ||
| 0 | VINP = 0 | 0 | 0000 0000 | 0 | 0000 0000 |
| VINP = VDD/2 | +2047 | 0000 07FF | +2,146,435,072 | 7FF0 0000 | |
| VINP ≥ VDD | +4095 | 0000 0FFF | +4,293,918,720 | FFF0 0000 | |
| 1 | VINP – VINN ≦ – VDD | -2048 | FFFF F800 | -2,147,483,648 | 8000 0000 |
| VINP – VINN = -VDD/2 | -1024 | FFFF FC00 | -1,073,741,824 | C000 0000 | |
| VINP – VINN = 0 | 0 | 0000 0000 | 0 | 0000 0000 | |
| VINP – VINN = VDD/2 | +1023 | 0000 003FF | +1,072,693,248 | 3FF0 0000 | |
| VINP – VINN ≥ VDD | +2047 | 0000 007FF | +2,146,435,072 | 7FF0 0000 | |