16.4.3 Sampling and Conversion Timing

The ADC module is clocked from the Clock Generator 6. This input clock is divided by four to get the analog core clock (T_AD). The conversion takes two ADC analog core clock cycles. The input module clock frequency must be in a range between 32 MHz (8 MHz core clock or 4 MSPS conversion rate) and 320 MHz (80 MHz core clock or 40 MSPS conversion rate).

Each channel can be configured for a different sampling time using SAMC[4:0] bits (ADnCHxCON1[20:16]).

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