6.2.17 NVM ECC Value Register

Name:	NVMECCVAL
Offset:	0x3040


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
								ECCVAL[8]
Access								R/HS
Reset								0


Bit	7	6	5	4	3	2	1	0
	ECCVAL[7:0]
Access	R/HS	R/HS	R/HS	R/HS	R/HS	R/HS	R/HS	R/HS
Reset	0	0	0	0	0	0	0	0

Bits 8:0 – ECCVAL[8:0] Error Correcting Code for the Data bits

These bits register the Error Correcting Code associated with the NVM read data (taking Fault injections into account) when the SEC or DED bit is set in the NVMECCSTAT register.

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