6.2.19 NVM CRC Control Register
| Name: | NVMCRCCON |
| Offset: | 0x3048 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| DELAY[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CRCEN | START | CRCIDL[1:0] | |||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| OM | CRCEC[1:0] | ||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
Bits 23:16 – DELAY[7:0] Delay between CRC accesses bits
Bit 15 – CRCEN Enable CRC Function bit
| Value | Description |
|---|---|
1 |
CRC function enabled. |
0 |
CRC function disabled. |
Bit 14 – START Start CRC calculation bit
| Value | Description |
|---|---|
1 |
Start CRC calculation (CRC in progress). |
0 |
CRC calculation complete (CRC function idle). |
Bits 9:8 – CRCIDL[1:0] Idle Operation Control bits
| Value | Description |
|---|---|
| 3 | Reserved |
| 2 | CRC operates in Idle mode and is stopped in CPU Run mode. |
| 1 | CRC operates in CPU Run mode and is stopped in Idle mode. |
| 0 | CRC operates in CPU Run mode and Idle. |
Bit 4 – OM Output Mode bit
| Value | Description |
|---|---|
1 |
CRC-32 state with neither padding nor final XOR |
0 |
CRC-32 checksum |
Bits 1:0 – CRCEC[1:0] CRC Error Code bits
| Value | Description |
|---|---|
| 3 | Invalid address (start address greater than end address) |
| 2 | Flash ECC DED error |
| 1 | Security access control violation |
| 0 | No error |