FPU WAR Hazards

WAR (Write-After-Read) anti-dependency hazard can occur should the pipeline allow read and write execution to be out of (instruction sequence) order. That is, a WAR hazard will arise whenever an instruction writes to a register before the same register is read by a prior instruction. That is, the read and write occur out of execution order resulting in the (older) read instruction ultimately using the (later) write data which would be incorrect.

Under normal sequential execution conditions, a WAR hazard should never arise because the read of all older instructions always precedes the writes of later ones. However, a WAR hazard can arise within the coprocessor pipeline when a slow instruction (e.g., FPU FSIN) has a result data dependency (RAW hazard) with a later instruction, and that later instruction is followed by a MOVWCR or POPCR instruction that targets the same register as the dependency. This is because the dependency will force an FPU pipeline stall until the result data is available and the RAW hazard is resolved, but the MOVWCR or POPCR move instructions (which do not execute using the FPU pipeline) will not be stalled. Consequently, it is possible that the write from the MOVWCR or POPCR instruction would occur prior to the stalled instruction continuing execution (after the RAW hazard). The write would then be overwritten by the FPU pipeline and, therefore, lost. This scenario is detected as a WAR hazard and prevented from happening by stalling the most recent write, such that the write order remains correct. CPU to FPU move instructions that do not target the register involved in the stall will still execute as normal (i.e., without stalling).

The coprocessor must, therefore, detect the possibility of such a hazard and force in-order execution of all dependent instructions by stalling the most recent CPU write instruction in the W-stage until after the prior read is completed.

An example WAR hazard and its resolution is as follows: A RAW hazard between the FSIN.s and FMOV.s instructions will stall FMOV.s to resolve the hazard (stall cycles shown in green), but this will also set the pipeline up for a possible WAR hazard because the subsequent MOVWCR instruction is not prevented from continuing execution.

As is the case in this example, should the MOVWCR instruction destination be the same F-reg as that used by the FMOV.s as a source, the MOVWCR must be prevented from writing until the prior (FSIN.s) has been able to forward the write data to the MOV.s RD-stage. The FSIN.s and MOVWCR enter their respective write stages together, and the FPU prioritizes the CPU write, maintaining correct write ordering. This results in a one-cycle stall of MOVWCR instruction to resolve the hazard.