2.7.2.17 Auxiliary Fault Status Register

The AFSR contains additional system fault information. See the register summary in Table 2-44 for its attributes.

This register is read, write to clear. This means that bits in the register read normally, but writing 1 to any bit clears that bit to 0.

The bit assignments are:

Table 2-64. AFSR Bit Assignments
Bits	Name	Function
[31:0]	IMPDEF	Implementation defined. The bits map to the AUXFAULT input signals.

Each AFSR bit maps directly to an AUXFAULT input of the processor, and a single-cycle HIGH signal on the input sets the corresponding AFSR bit to one. It remains set to 1 until you write 1 to the bit to clear it to zero.

When an AFSR bit is latched as one, an exception does not occur. Use an interrupt if an exception is required.